1. Field of the Invention
This invention relates generally to clock multiplexing, and more particularly to a symmetric glitch free clock multiplexing circuit with asynchronous switch control.
2. Description of the Prior Art
Many system-on-chip (SOC) circuits currently on the market consist of multiple dedicated processing modules that interact harmoniously with each other to achieve the desired functionality. SOC designs become very attractive in the advance of wireless and handheld devices because they deliver lower cost, power consumption and form factor.
A significant challenge associated with integration of different functional modules in a SOC is presented by modules operating at different clock frequencies. Further, such integration can become even more complex when an individual module can also be operating at different clock frequencies depending on the overall state of the SOC device. As many designers carefully squeeze out every last pico-second from the circuit datapath, any uncertainty that might affect the input clock can spell disaster to the SOC device functionality. Many embedded electronic systems, for example, frequently require certain circuit modules to be turned on and off or to be running at different clock frequencies depending on the state of the systems. These clock frequencies might not be synchronous to each other, nor to the control signal that commands the frequency change. Even when these clocks are synchronous, the phase differences might not be always known, which can create a glitch or short cycled output clock that can potentially cause problems in the circuit.
It is therefore advantageous and desirable to provide a system and method for allowing a SOC circuit to freely turn on or off and switch clock frequencies to any associated circuit modules without causing any module malfunction due to glitches in the clocking system.
The present invention is directed to a symmetric glitch free clock multiplying circuit that allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the perspective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa. More importantly, the complete switch over only takes as low as two cycles of the targeted clock once the active clock is turned off, when switching from slow to fast clock.
According to one embodiment, a clock multiplexer comprises: a first cascaded synchronization circuit configured to generate a first output clock in response to a reference clock and a switch control signal; a second cascaded synchronization circuit configured to generate a second output clock in response to a fast clock and the switch control signal; and a combinational element configured to generate a substantially glitchless output clock in response to the first output clock and the second output clock.
According to another embodiment, a method of generating substantially glitch free clock switching comprises the steps of: providing a first cascaded synchronization circuit configured to generate a slow internal clock in response to a reference clock and a switch control signal that is asynchronous to the reference clock; providing a second cascaded synchronization circuit configured to generate a fast internal clock in response to a fast clock and the switch control signal; and generating a substantially glitch free output clock in response to the slow internal clock and the fast internal clock.
According to yet another embodiment, a clock multiplexer comprises: a first synchronization circuit configured to generate a slow internal clock in response to a reference clock and a switch control signal; a second synchronization circuit configured to generate a fast internal clock in response to a fast clock and the switch control signal; and at least one logic device configured to generate a substantially glitch free output clock that is devoid of short cycling, in response to the slow internal clock and the fast internal clock.